Meta partners with Google in multibillion‑dollar AI‑chip rental deal, sources say.

Meta’s decision to abandon its in‑house “M2” training accelerator last month was driven by “design roadblocks” that made the chip’s power‑efficiency and yield targets unattainable, according to a report from GuruFocus. The setback left Meta with a short‑term capacity gap as it races to scale LLM inference and fine‑tuning workloads across its family of AI products, from Llama 2 to the upcoming “Meta AI” suite. Rather than rebuild a custom silicon pipeline, the company turned to Google’s Tensor Processing Units (TPUs), which it will now lease on a multibillion‑dollar basis. SiliconANGLE confirms that the agreement covers the latest generation of Google’s TPU‑v5e accelerators, the same hardware that powers Google’s own Gemini models and internal AI services. The deal is structured as a long‑term rental, allowing Meta to tap Google’s high‑density, low‑latency interconnect fabric without committing to upfront capex.

The rental model mirrors Google’s recent strategy of monetizing its AI hardware through “cloud‑native” offerings, a move that has already generated billions in revenue from enterprise customers. The Information, as cited by Finextra Research, says the contract is valued in the “low‑single‑digit‑billion‑dollar” range and spans several years, with usage tiers tied to Meta’s projected compute demand. By leasing TPUs, Meta can immediately access up to 6 GW of compute power—a figure that matches the capacity it announced for AMD GPUs in a separate CNBC report and complements its expanded Nvidia partnership announced earlier this quarter. The combined hardware portfolio gives Meta a heterogeneous compute stack: Nvidia’s H100 for dense matrix operations, AMD’s MI250X for mixed‑precision workloads, and Google’s TPUs for transformer‑centric inference pipelines.

From a technical standpoint, Google’s TPU‑v5e delivers roughly 275 TOPS per chip at 400 W, with a 3‑D stacked memory subsystem that reduces data movement latency by 30 % compared to conventional GPU DRAM architectures. The chips also feature a proprietary “systolic array” design that excels at the attention‑mechanism kernels dominant in LLM inference. Meta’s engineering teams, which have been iterating on model parallelism and pipeline parallelism to squeeze performance out of heterogeneous hardware, will now be able to offload the bulk of transformer inference to the TPUs, freeing GPU capacity for vision‑centric models and multimodal training runs. According to Seeking Alpha, the deal includes a “co‑design” clause that gives Meta early access to Google’s next‑gen TPU roadmap, potentially allowing the two firms to align on tensor‑core instruction sets and memory bandwidth requirements.

The partnership also has strategic implications for the broader AI‑chip market. Google and Meta have historically been rivals—Meta’s AI research arm has long relied on Nvidia GPUs, while Google’s internal AI workloads run almost exclusively on its own TPUs. By bridging that divide, the agreement signals a maturing ecosystem where scale‑up demands outweigh competitive posturing. Bloomberg’s coverage of Meta’s $14 billion AI‑infrastructure deal with CoreWeave underscores the intensity of the compute arms race; Meta is now hedging its risk by diversifying across three major hardware vendors. Analysts note that the multibillion‑dollar TPU rental commitment could accelerate Google’s push to open its AI‑chip ecosystem to non‑Google customers, a market segment that has been dominated by Nvidia and, more recently, AMD.

Finally, the shift away from custom silicon may affect Meta’s long‑term roadmap for AI‑specific hardware. While the company has not ruled out future in‑house designs, the immediate priority is to deliver reliable, high‑throughput inference for its expanding suite of consumer‑facing AI features—reactions, text generation, and augmented‑reality overlays. By leveraging Google’s proven TPU infrastructure, Meta can meet those service‑level objectives while preserving cash for content‑moderation, safety research, and the next generation of LLMs. The move also buys Meta time to evaluate whether the lessons learned from the aborted M2 chip can be applied to a more modular, perhaps ASIC‑agnostic, approach to AI acceleration in the years ahead.