Intel unveils Panther Lake‑H die shot, revealing 18‑core compute tile and Xe3 GPU in new

Intel’s Panther Lake‑H silicon is built around a three‑tile architecture that mirrors the company’s “chip‑on‑wafer‑package” strategy first seen in Alder Lake. The compute tile, fabricated on Intel’s 18 Å process, houses four high‑performance “Cougar Cove” P‑cores with 3 MiB of L2 cache each, eight efficiency “Darkmont” E‑cores running up to 3.8 GHz, and four low‑power “Darkmont LPE” cores capped at 3.7 GHz, according to the die‑shot analysis published by Kurnal‑Insights and reported by Tom’s Hardware. The tile also contains an 18 MiB L3 cache split into three slices that sit close to the P‑core and E‑core clusters, while the LPE cluster is positioned farther away, a layout that enables Intel to disable a defective slice without crippling the entire die. In addition, three separate NPU slices each carry 4.5 MiB of cache, further compartmentalizing compute resources and improving yield.

The Xe3 graphics tile, measured at roughly 8.14 × 6.78 mm, integrates a next‑generation Xe‑architecture GPU that Intel says will support the company’s “Xe‑HPC” instruction set and hardware‑accelerated ray tracing. While Intel has not disclosed raw shader core counts, the die‑shot shows a dense array of execution units that share a dedicated 8 MiB memory‑side cache (MSC) with the DDR5/LPDDR5X‑9600 memory controller. Tom’s Hardware notes that the MSC functions as a buffer to reduce latency and bandwidth pressure when multiple cores or NPUs simultaneously access RAM, a design echoing Intel’s earlier CrystalWell L4 cache but distinct from Apple’s system‑level cache, which operates as a unified last‑level cache for the whole SoC.

The I/O tile, the largest of the three at 12.44 × 4.00 mm, contains the 128‑bit DDR5/LPDDR5X‑9600 memory controller, the 8 MiB MSC, and a suite of integrated media and display engines. According to the annotated die‑shot, the memory controller’s high‑speed interface is paired with the MSC to smooth traffic bursts from the 18‑core compute tile, a necessity given the tile’s aggressive clock rates—up to 5.1 GHz on the P‑cores. The I/O tile also routes PCIe 5.0 lanes, Thunderbolt 4, and USB4 connections, consolidating the platform’s external bandwidth in a single package.

Intel’s decision to expose the die‑shot at this stage signals confidence that the Panther Lake‑H family can meet the performance expectations set by the Core Ultra 300‑series launch in January. By revealing the exact core mix and cache topology, Intel is providing OEMs and system integrators with the data needed to fine‑tune thermal and power budgets for high‑end laptops and mobile workstations. The three‑slice L3 cache and modular NPU design also suggest a yield‑friendly approach: defective slices can be disabled, allowing Intel to ship functional dies even when a portion of the silicon is compromised—a tactic that could improve overall fab efficiency and reduce per‑unit cost.

Analysts observing the die‑shot note that the 18‑core configuration places Panther Lake‑H squarely in competition with AMD’s Ryzen 9 8000‑series mobile parts, which also blend high‑performance and efficiency cores but rely on a monolithic die rather than Intel’s tiled approach. The presence of a dedicated Xe3 GPU, however, gives Intel a potential edge in workloads that benefit from integrated graphics acceleration, such as AI‑enhanced media processing and real‑time ray tracing in thin‑and‑light form factors. While Intel has not disclosed benchmark numbers, the combination of a 5.1 GHz P‑core cluster, a sizable L3 cache, and a high‑bandwidth memory subsystem suggests that Panther Lake‑H could deliver single‑thread performance comparable to desktop‑class CPUs while maintaining the power envelope required for premium laptops.

Overall, the die‑shot confirms that Intel is doubling down on its heterogeneous compute strategy: a high‑frequency P‑core island for peak performance, a larger pool of efficiency cores for multithreaded workloads, and a purpose‑built graphics tile that leverages the same 18 Å process node. If the architecture lives up to its specifications, Panther Lake‑H could become the cornerstone of Intel’s 2026 mobile roadmap, offering OEMs a compelling alternative to AMD’s offerings and reinforcing Intel’s claim that its “tile‑based” design can deliver both performance and yield advantages in the competitive high‑end laptop market.