AMD Zen 6 Leak Shows Ten‑Core CPU with 32 MB L3 Cache Scoring on Geekbench

The benchmark, posted by the BenchLeaks bot on Tom’s Hardware, shows a ten‑core, 20‑thread Zen 6 “Medusa Point” sample scoring 1,210 points in single‑core and 7,323 points in multi‑core Geekbench 6, with a clock range of 1.37‑2.01 GHz (average 1.44 GHz)【Tomshardware】. Those numbers alone are modest, but the data point is significant because it confirms the existence of a low‑power, 28 W mobile chip that departs from AMD’s traditional Strix Point design. The OPN “100‑000001713‑31_N” links the part to the FP10 BGA socket, which has been associated with the upcoming FP10 platform in previous leak chains, and the “Plum‑MDS1” system identifier further ties the sample to the Medusa Point family, as noted by Tom’s Hardware【Tomshardware】.

The most striking specification is the 32 MB L3 cache attached to the ten‑core die. Current Zen 4 mobile parts, including the Ryzen AI Max and the “Fire Range” laptop CPUs, allocate 32 MB of L3 per CCD, but they never combine ten cores on a single CCD. The presence of a full 32 MB L3 cache on a ten‑core die therefore implies a new CCD layout unique to Zen 6, corroborating the claim that Medusa Point will be built on a chiplet architecture rather than the monolithic designs of Strix and Gorgon【Tomshardware】. This cache size also suggests a potential boost in per‑core bandwidth, a key metric for laptop workloads that rely on fast data access, such as AI inference and content creation.

Leaked ordering‑part‑number data from NBD Data further clarifies the chip’s configuration. The “1713” suffix in the OPN appears in NBD’s shipping logs as a “4C4D” part, which Tom’s Hardware interprets as four high‑performance Zen 6 cores paired with four efficiency‑focused Zen 6C dense cores【Tomshardware】. If accurate, this hybrid core arrangement mirrors Intel’s recent “big‑LITTLE” strategies and would give AMD a new lever for balancing performance and power in thin‑and‑light laptops. The 28 W TDP aligns with the FP10 platform’s target envelope, positioning Medusa Point as a direct competitor to Intel’s 28 W “Alder Lake‑P” and “Raptor Lake” mobile parts slated for 2026.

The leak also sheds light on AMD’s broader roadmap. While the company’s public roadmap has focused on Zen 4 and the upcoming Zen 5 desktop and server chips, the appearance of a Zen 6 mobile sample indicates that AMD is already preparing a next‑generation mobile architecture for launch in late 2026 or early 2027. This timing dovetails with the company’s historical cadence of introducing a new Zen generation roughly every 18‑24 months, as seen with Zen 3’s 2020 debut and Zen 4’s 2022 rollout【Ars Technica】. By moving Zen 6 to the mobile segment first, AMD may be aiming to capture market share in the high‑performance laptop space before the Zen 6 desktop parts arrive, a strategy that could pressure Intel’s mobile dominance.

Analysts will likely watch how the 32 MB L3 cache and hybrid core design translate into real‑world performance once the chip reaches production. If the cache delivers the expected latency reductions and the efficiency cores effectively offload background tasks, Medusa Point could offer a compelling alternative to Intel’s 13th‑generation mobile offerings, especially for OEMs seeking a balance between battery life and sustained performance. However, the modest clock speeds observed in the leak—capped at roughly 2 GHz—suggest that AMD may still be fine‑tuning the power‑performance envelope, and the final product could differ substantially from the sample shown on Geekbench【Tomshardware】.